With the rapid development of electronic information technology, people have increasing demands on the speed of electronic products. The speed of electronic products has become one of the most important indicators for electronic circuits. Therefore, more and more challenges have been posed for circuit designers.
Nonvolatile memory (NVM) is a commonly-used memory. Specifically, an NVM may allow data to be stored even after power failure. Using flash memory as an example, the design of high-speed flash memory faces increasing demands on the read speed of the memory. The data read time for an NVM (for example, a flash memory) usually includes four parts associated with address decoding, bit-line pre-charging, memory-cell current amplifying, and data comparison and output, respectively. Problems arise, however, because the NVM has a relatively long data read time. This may not meet the high-speed application requirements for NVM. Therefore, the data read time for the NVM needs to be shortened in order to improve the operation speed of the NVM.
Among the above four parts of the data read time for an NVM, the time period associated with address decoding as well as the time period associated with data comparison and output may account for a small portion of the overall data read time. Moreover, the time period associated with memory-cell current amplifying is mainly process dependent, and may hardly be shortened. Therefore, among the four parts of the data read time for an NVM, the time period associated with bit-line pre-charging may be a part that can be possibly shortened.
The disclosed NVMs and reading methods thereof are directed to solve one or more problems set forth above and other problems in the art.